AMD Announces Zen 4 Microarchitecture Under Development

Ceria Alfonso
Noviembre 8, 2018

Based on AMD's 25 percent improvement in performance with Vega 7nm, Zen 2 could compete directly with Intel on clockspeed, and other enhancements to the core architecture are likely as well.

According to revealed specifications, the 7nm EPYC Rome datacenter CPU will pack up to 64 Zen 2 cores with 128-threads, offer increased instructions-per-cycle, as well as bring leadership in compute, I/O, and memory bandwidth.

More information on the announcements made during the event are available on the AMD Next Horizon page.

AMD claims a doubling of throughput and support for processing 256-bit floating point instructions, as well as better branch prediction and much better power efficiency. That could soon change.

A little context: Intel's top-of-the-line 28-core Xeon Skylake processor now offers about three times the floating point performance of the first-generation 32-core EPYC 7601 processor. AMD boasts that a single Rome EPYC chip can outperform Intel's last-gen Xeon Scalable 8180M in dual-socket configuration when running the ray-tracing C-Ray benchmark, however this has yet to be confirmed via independent testing. A few days ago, Intel claimed that its upcoming 48-core HPC Xeon processor, known as Cascade Lake Advanced Performance (AP), would deliver 3.4 times the floating point performance on Linpack as this same EPYC chip.

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Are you a techie who knows how to write? 'Combining world-class performance and a flexible architecture with a robust software platform and the industry's leading-edge ROCm open software ecosystem, the new AMD Radeon Instinct accelerators provide the critical components needed to solve the most hard cloud computing challenges today and into the future. Papermaster summed it up thusly: "We're in the business of high performance". One die of 8 Zen 2 cores (without any IO) is less than half the size of one full Summit Ridge die, the original Zen die.

This will make EPYC "Rome" the world's first 7-nanometer datacenter processor. But because of continued delays in Intel's 10nm effort, AMD lucked out; it will be shipping some of the fastest and most power-efficient silicon in the datacenter next year.

Rome takes a more modular approach than Naples, sporting a central 14nm I/O die with eight memory controllers and proprietary Infinity Fabric ports. For example, the I/O and Infinity Fabric chiplets in Rome are implemented on a 14nm process, since unlike the execution units, they don't need the same level of transistor density.

AMD was also focused on providing a stable roadmap revealing that Zen 2 EPYC Rome is sampling now, with availability expected in 2019, while Zen 3 Milan is on track and should come sometime in 2020. A Zen 4 processor is also in the works, although no timeline was given for its debut.

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